網路上教的範例~除法器

module div(r1,r2,r3,pb,clk,x,y,ready) ;

input pb , clk;
input [3:0] x,y;
output [3:0]ready,r3,r2,r1;
wire pb;
wire[3:0] r1,r2,r3;
reg[3:0] r1,r2,r3,ready;
always
begin
@(posedge clk)
r1<=x ; r2<=0 ; ready=1; if (pb) begin while(r1>=1)
begin
@(posedge clk)
r1<=r1-y; @(posedge clk) r2<=r2+1; @(posedge clk) r3<=r2; end end end endmodule

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